Indigo2 and POWER Indigo2 Technical Report

• pipelined GIO64 bus slots

• two channels of Fast SCSI-2, lOBase-T Ethernet, and PS/2 standard keyboard and mouse ports

• four EISA bus connectors.

• an advanced system architecture

  
  The Indigo2 provides an easy upgrade path for newer and faster CPUs; the CPU and the second- level cache is mounted on an easily changed CPU module which can be swapped without changing the rest of the system board.

  The Indigo2 system board's main memory capacity is a full 384 MB of DRAM. Because the system board replaces SIMM-mounted DRAM interleave controllers with motherboard mounted DMUX chips, main memory is implemented with standard 36-bit-wide DRAM SIMMs.

  The block diagram illustrated in Figure 2 illustrates the Indigo2 system board.

  

  
  The system board contains four functional sections, as illustrated in Figure 2:

  • The processor core contains the CPU and secondary cache. This section is designed to take advantage of the very fast CPU speed and the 64-bit data bus. The CPU, second-level cache, oscillator, and EEPROM of this section have been separated and mounted on a CPU module for easy replacement.

  • Main memory, which contains DRAM and supporting circuitry. This section is also designed to provide 64-bit-wide CPU access to DRAM and implements the memory interleave function with custom DMUX chips in the base system hoard. This allows the use of standard, off-the-shelf memory SIMMs.

  • The I/O system, which contains peripheral ports and hardware designed to handle incoming and outgoing data with minimal CPU overhead.

  • The audio system, an audio system architecture which utilizes the HAL2 ASIC to perform the audio I/O functions replacing the need for a digital signal processor.

    
    

  Three buses connect parts of the CPU board:
  • The CPU bus, which connects the CPU module to the bus control hardware. This bus is 64- bits wide to support the CPU and its 64 bit datapath.

  • The GIO64 bus, which is the main system bus connecting the processor core, main memory, I/O system, expansion slots, and graphics board.

  • A 32-bit wide EISA bus connects the GIO64 to the EISA expansion slots.

  • The CPU bus, GIO64 bus, and EISA bus have separate clocks and run at different speeds so that each part runs at maximum capability; the CPU and other chips can be upgraded independently as technology improves.

    
    

  Silicon Graphics developed custom ASICs to aid communication between the system and the buses:
  • The MC ASIC performs many functions, such as the GIO64 bus arbiter, which provides an interface between the CPU and the GIO64 bus. It is also the memory controller, allowing direct memory access (DMA) by devices other than the CPU.

  • DMUX ASICs are data path chips, controlled by the MC chip, that isolate the CPU bus from the GIO64 bus. They also perform the memory interleaving functions.

  • The HPC3 ASIC provides an interface to peripheral I/O, the audio system, and other devices on the peripheral bus, connecting them to the GIO64 bus.

  • The EIU ASIC provides an interface between the GIO64 bus and the Intel EISA chip set. The EIU performs bus protocol conversion, selective byte swapping, EISA arbitration, and bus throttling for EISA devices.

  • The INT2 ASIC is the system timer and interrupt controller chip.

  • The EPP1 ASIC is a high-performance, bidirectional parallel port chip that can transfer data by DMA to minimize host CPU interaction.

  • The REX or HQ2 ASIC, located on the graphics board, connects the entire graphics board to the GIO64 bus.

    
    

3.1.1 MIPS R4400SC CPU Module

This MIPS R4400SC CPU (shown in Figure 3) contains the main processor, a floating point processor, a 16 KB onboard instruction cache, and an 16 KB onboard data cache. The R4400SC CPU also provides a dedicated interface to a 1 MB second-level cache. The 200 MHz R4400SC chip's external clock rate is 100 MHz, but it runs internally at 200 MHz. The 64-bit data and instruction paths to the chip's caches bring in data and instructions at a speed which minimizes cache misses and CPU idling.

System performance estimates of the 200 MHz R4400SC exceed 180 MIPS (Dhrystone 1.1), 34 MFLOPS (double precision), 124 SPECfp92, and 116 SPECint92.

FIGURE 3 The functional sections of the MIPS R4400SC CPU.

The R4400SC uses superpipelining to achieve the fast internal speed. In normal pipelining, the CPU breaks each instruction into separate one-cycle steps (usually fetch, read, execute, memory, and write back), and then executes instructions at one-cycle intervals.

At the fast R4400SC CPU clock rate, some instruction steps such as cache reads and writes can't execute in a single pipelined cycle. Superpipelining executes each of these critically slow steps in a single cycle to provide higher throughput. To do so, it first breaks instruction steps into substeps. The substeps are then pipelined in a process separate from standard pipelining, which executes the full step in a single cycle. R4400SC superpipelining is optimized so that it requires little control logic and instruction structure.

The R4400SC CPU supports the MIPS 1 instruction set (used by the R3000A CPU), the MIPS 2 instruction set and the MIPS 3 instruction set. Data pathways in MIPS 3 are 64 bits wide, giving the system the ability to load and store full floating point double words in a single machine cycle. The MIPS 3 instruction set also contains synchronization and advanced cache control primitives.

This MIPS R44600 CPU (shown in Figure 3) contains the main processor, a floating point processor, a 16 KB onboard instruction cache, and an 16 KB onboard data cache. The R4600 CPU also provides a dedicated interface to a 1 MB second-level cache. The R4600 chip's external clock rate is 66.67 MHz, hut it runs internally at 133 MHz. The 64-bit data and instruction paths to the chip's caches bring in data and instructions at a speed which minimizes cache misses and CPU idling.

System performance estimates of the 133 MHz R4600 exceed 169 MIPS (Dhrystone I.I), 20 MFLOPS (double precision), 72 SPECfp92, and 109 SPECint92.

FIGURE 4 The functional sections of the MIPS R4600 CPU.

The R4600 uses a 5-stage pipeline similar to the R3000. This pipeline is simpler than the 8-stage superpipeline used in the R4400 and is more efficient (fewer pipeline stalls) in terms of branch and load latency.

The internal pipeline of the R4600 operates at twice the frequency of the input clock. The CPU achieves high throughput by pipelining cache accesses, using virtual-indexed primary caches, and allowing the latency of certain functional units to span more than the internal clock cycle.

The R4600SC CPU supports the MIPS 1 instruction set (used by the R3000A CPU), the MIPS 2 instruction set and the MIPS 3 instruction set. Data pathways in MIPS 3 are 64 bits wide, giving the system the ability to load and store full floating point double words in a single machine cycle. The MIPS 3 instruction set also contains synchronization and advanced cache control primitives.

For information on the R8000 CPU, see Section 7 "The R8000 POWER Indigo2."

The MC ASIC, the Memory Controller (shown in Figure 9), is a custom Silicon Graphics chip connected to the CPU module by the CPU bus. It's also connected to the GIO64 bus (the system bus), and has address and control lines connected to main memory. It performs many functions:

• It provides an interface between main memory and the CPU core

• It serves as a DMA (Direct Memory Access) controller for all memory requests from the graphics system or any other devices on the GIO64 bus

• It acts as a system arbiter for the GIO64 bus

• It provides single-word accesses for the CPU to GIO64 bus devices and to the graphics system

• It passes on interrupts from the INT2 ASIC to the CPU

• It initializes the CPU on powerup, executes CPU requests, refreshes memory, and checks data parity in memory

  
  

FIGURE 5 A block diagram of the MC ASIC. The MC runs the system bus, handles memory access for CPU and GIO64 devices, works as a DMA controller, and fulfills other miscellaneous functions.

Of special note is the MC's ability to support Virtual DMA requests from processes running on the CPU. The process can also set up a DMA descriptor in MC and then request the DMA engine to start. The memory addresses used in the DMA descriptor are virtual memory addresses which the MC translates (using a TLB and UNIX page tables) to physical memory addresses. When the DMA operation is finished, an interrupt may be generated (if the interrupt is enabled in MC) to inform the CPU.

The DMUX ASICs are a two-chip slice of a data crossbar between the CPU, main memory, and the GIO64 bus. The two DMUX chips are, together, a data path with control signals generated by the MC. They isolate the CPU bus from the memory system and the GIO64 bus. They also contain synchronization FIFOs to perform flow control between the various subsystems, and they interleave main memory to increase peak memory bandwidth.

The INT2 ASIC is connected to the MC chip instead of directly to the CPU. The MC chip passes on all interrupts from INT2 to the CPU.

The GIO64 is the Indigo2 workstation's main system bus and is designed for very high speed data transfer. It connects the Indigo main systems: the processor core, main memory, the I/O systems, the graphics system, and any boards plugged into the GIO64 expansion slots. It is a synchronous, multiplexed address/data, burst mode bus that is clocked independently of the CPU.

• bus protocol conversion

• selective byte swapping

• EISA arbitration

• bus throttling for EISA devices

  
  

• 25 MBytes/second at GIO speed of 25 MHz

• 33.3 MBytes/second at GIO speed of 33 MHz

  
  

EISA Bus Controller

• Support for EISA/ISA memory-i/o cycles

• Supports EISA/ISA wait/no-wait cycles

• Supports EISA Burst cycles

• Generates EISA signals for ISA masters

• Supports Type A,B,C, DMA cycles

• Supports compatible DMA cycles

• Controls EBB during byte assembly/disassembly

  
  

• Provides Enhanced DMA functions

• Provides EISA Interrupt control

• Provides EISA Counter/Timer

• Provides EISA bus timeout logic

  
  

• Provides data buffering and swap functions

• Provides address buffering and latch functions

  
  

FIGURE 6 Memory on the R4400SC/R8000 CPU board interleaves SIMM strips in banks of four, and connects them to the CPU and the GIO64 bus with DMUX and MC chips.

• 96 MB using all 8 MB SIMMs

• 192 MB using all 16MB SIMMs

• 384 MB using all 32 MB SIMMs

• 640 MB using a combination of 64 MB and 32 MB SIMMs

  
  

The HPC3 ASIC, the High Performance Peripheral Controller, is a custom Silicon Graphics chip that connects to the GIO64 bus and directly to several of the I/O ports. It is the heart of the I/O system, and quickly transfers data between main memory and a rich collection of peripheral devices, at the peak rates of such devices. It uses minimum bandwidth on the GIO64 bus, freeing the bus for other data transfers.

The HPC3 permits fast data interchange between peripheral devices and main memory without involving the CPU, improving both CPU and peripheral performance. For each peripheral device, the HPC3 provides an independent FIFO data buffer, and supports DMA to main memory through the GIO64 bus and the MC ASIC. It provides interfaces to the serial ports and other devices through the peripheral bus.

The Ethernet interface consists of both an AUI and a 10BASE-T Ethernet port supported by a controller that is connected directly to the HPC3 ASIC. The interface automatically selects between the AUI and 10Base-T ports; the user does not have to manually change a DIP switch. The HPC3 supplies the logic required to retransmit packets when collisions occur and to manage the interface's 64-byte FIFO buffer. When the HPC3 receives a packet, it interrupts the CPU after it writes the packet into memory. When transmitting, it interrupts the CPU when a packet is successfully sent or when 16 transmission attempts have all failed.

The Fast SCSI-2 interface consists of one internal channel and one external channel. The internal channel connects three internal SCSI devices. The external channel provides an external high-density SCSI port on the rear of the central unit. Each Fast SCSI-2 channel is supported by a SCSI controller connected directly to the HPC3 ASIC. The HPC3 uses two FIFO buffers to enable hurst use of the GIO bus.

The parallel port interface provides a bidirectional Centronics parallel port to connect printers, plotters, scanners, and other similar devices. The port is connected to the peripheral bus and provides a FIFO buffer used to transfer data between main memory and the parallel port at up to 1.0 MB/sec.

The peripheral bus (P-Bus) is a 20-bit address, 16-bit data bus used by the HPC3 for additional peripheral support. It connects the boot PROMs, a real-time clock, the timer, two serial ports, a mouse port, a keyboard port, the EPPI ASIC parallel port interface and the audio system through the HAL2 ASIC. There is a 384 byte memory that is shared by all of the peripheral bus devices to buffer DMA transfers to and from memory.

The serial interface consists of two serial ports, controlled by a DUART chip that connects to the Peripheral Bus. They can be configured as EIA-232 standard devices or as external Apple Macintosh compatible connectors that can connect to common Macintosh peripherals such as laser printers and scanners. The serial ports support a transfer rate of up to 38.4 KBaud.

The PS/2 standard keyboard and mouse are controlled by industry-standard hardware and firmware, ensuring compatibility with a wide variety of third party input devices.

FIGURE 7 Indigo2 Audio Block Diagram

• Stereo line level analog audio input and output

• Stereo headphone output

• Built-in speaker

• AES/EBU digital audio input and output

• Sampling rates of 48 kHz, 44.1 kHz, 32 kHz, 16 kHz, 8 kHz, and more

• Microphone input with DC power

• Simultaneous input and output

• Independent input and output rates

• Output rate may be synchronized to the digital input rate

• Professional quality analog signal processing

• Silicon Graphics Audio Library (AL) API

• Low latency operation for highly interactive applications

  
  

• Microphone input now supports stereo microphones

• Time-stamped samples
  • utime format time stamps on every sample frame

  • time stamps are synchronized with CPU time base

  • additional bits give resolution to O.I microsecond

• Non-audio bit tagging on audio samples
  • left and right analog clip indicator bits

  • P, C, U, and V bits for digital audio samples

• Four channel mode supports four analog channel input and four analog channel output, simultaneously, at full speed

• Analog audio input and serial digital audio input may occur simultaneously

• Analog audio output and serial digital audio output may be independent

• Analog audio input may be synchronized to digital audio input

• Sampling time base is generated by Bresenham's algorithm, allowing near continuous choice of sample rates

  
  

The Indigo2 audio system is built around a central controller chip, the HAL2 ASIC, two audio CODEC chips, an AES transmitter chip, an AES receiver chip, a microphone input circuit, a headphone/speaker amplifier circuit, and a four-channel-mode output switch.

The HAL2 chip is a 1 micron, 28k gate CMOS gate array which contains the data path and control logic to interface the HPC3 peripheral bus and the audio devices on the module. The major functional blocks connected to the HAL2 are the two CS4216 CODECS, the CS8401 AES transmitter, the CS8411 AES receiver, the headphone and speaker gain circuit, the microphone input circuit, and the four-channel mode output switch.

Notable features of the HAL2 design include:

• Three independent clock generators
  • AES out

  • analog in

  • analog out

• Each of the clock generators can select from three different timebases

• The clock generators use Bresenham's algorithm to scale the input clocks by rational fractions

• The time stamping clock is generated from the same timebase as the unix utime

• Each audio device has its own DMA channel and clock generator

• The DMA channel allocation is configurable in software

• The audio devices attach with conventional 3-wire serial interfaces

• In 4 channel mode, data from all four channels goes over the same DMA channel guaranteeing synchronization

  
  

The Indigo2 audio system uses a pair of Crystal Semiconductor CS4216 stereo audio Codecs. These chips are highly integrated monolithic CMOS mixed-signal devices which make use of the latest signal conversion technology. Both the analog-to-digital converters (ADC) and digital-to- analog converters (DAC) are 64x-oversampling delta-sigma 16-bit converters. They also contain on-chip reconstruction and anti-aliasing filters, programmable input gain, and programmable input source switching. The filters' responses track the sampling rate, a significant advantage over the older fixed-response low-pass analog filter designs.

In the normal mode of operation, the Codec A DAC is used for analog output and the Codec B ADC is used for analog input. The Codecs can use independent sample-rate clock generators from the HAL2, so that the analog input sample rate and the analog output sample rate may be selected independently. The analog input (to Codec B) is selectable from either the line or microphone inputs under software control. The analog output signal (from Codec A) is routed both to line-out and to the stereo headphone/internal loudspeaker circuit. The user gets true line-level signal and a volume-adjusted headphone/loudspeaker output.

The Indigo2 audio system provides an enhanced mode of operation that extends the number of simultaneously active analog input channels from 2 to 4 and the number of simultaneously active analog output channels from 2 to 4.

In 4-channel mode, both Codecs are synchronized to the same sample rate and the Codecs are used simultaneously for input (ADC) and output (DAC). Codec A's input (ADC) comes from the microphone input, Codec B's input (ADC) from the line input. Codec A's output continues to be routed to the line output, but Codec B's output is routed at line-levels to the headphone jack.

The Indigo2 has an industry-standard, transformer-coupled, serial digital audio output that supports up to 24-bit stereo samples at all available sample clock rates. The audio and non-audio bits may be coded to support both professional and consumer standards (AES3, IEC958).

The Indigo has an industry-standard, transformer, coupled, serial digital audio input that supp up to 24-bit stereo samples at up to a 50 kHz sample rate. The sample rate clock recovered ft this input may he used to generate synchronized sample clocks for the Codecs and serial digi audio transmitter. All of the hits received in the serial digital channel including U, C, V. and P input to the computer. Both professional and consumer coding formats are supported by AES3, IEC958.

The Indigo2 comes standard with a high-quality, electret condenser monaural lapel microphone. The microphone is omnidirectional and has both a wide-frequency response and a large dynamic range.

The Indigo2 microphone input circuit provides DC power for active circuitry in microphones that require it, while retaining compatibility with other types of microphones. Powered microphones, such as the one supplied with Indigo2, use this DC power to drive a large low-impedance signal back to the audio circuitry, avoiding the problems commonly associated with low-level microphone signals and electrically noisy computer environments.

The microphone input circuit accepts both monaural and stereo microphones. In addition to the input source switching and software-controlled gain functions available in the Codecs, the DC power feature and a hardware 20 dB gain stage may be enabled and disabled via software control.

The internal speaker in the Indigo2 audio system outputs the sum of the left and right line-out channels. The speaker is shielded to protect the graphics and video monitors from the speaker's magnetic field. Speaker volume is software controlled.

The Indigo2 audio system provides a stereo headphone output connection, suitable for connecting standard headphones without need for external amplifiers. The headphone volume for each channel is software controlled. When a headphone is plugged into the connector, the internal speaker is automatically disconnected.